The present invention relates to integration of noise sensitive and noise generating circuits on a single die in a structural arrangement that minimizes noise coupling from the noise generating circuit to noise sensitive circuit.
A system-on-a-chip solution requires implementation of different function blocks are into a single silicon die. This creates potential problems of noise coupling between the noise generating and noise sensitive circuits. When a gate driver IC integrates more noise sensitive function blocks, it is important to avoid noise coupling a noise generating gate driver stage and other noise sensitive function blocks, e.g., analog circuits or PWM modulator.
Two kinds of noise couplings are present inside the gate driver IC, they are voltage induced capacitive coupling, and current and common stray impedance induced voltage coupling. The noise in the voltage induced capacitive coupling is caused by dV/dt transition of a floating well. Since the floating well having high-side driver has to be biased on a switching node, which has a large voltage transition, the dV/dt transition injects a current through a stray capacitance to the noise sensitive circuits.
This stray capacitance between the floating well and a substrate is inevitable. Therefore, combining the noise current injection with a stray inductance in power supply lines, the low-side voltage potential becomes noisy. As long as the noise sensitive blocks sit on the substrate, it is difficult to remove influences from a dV/dt induced noise injection.
The current induced noise coupling is caused by di/dt transition of a gate drive output stage. If the other functional blocks are sharing the same power supply, the noise voltage, created by the di/dt and stray inductance modulates the supply voltage, causes poor performance in noise sensitive circuits. The only way to avoid this noise injection is to separate power supply lines from each other. This, however, requires more pin outs. Even so, there will be a capacitive coupling remaining.